The present invention relates to computer systems, and more particularly, to a method and apparatus for alternating between a clock and an asynchronous event without loss of data during such changes.
It is now common for computers to be equipped with interface ports or communication buses. These buses exist for enabling communication between devices such as a host computer and one or more peripheral devices such as external disk drives, printers, and the like. Additionally, it is common for a peripheral device to utilize digital application specific integrated circuits (xe2x80x9cASICsxe2x80x9d) to receive data from or send data to other devices such as host computers. As the focus of the present invention is on an ASIC for a peripheral device, the peripheral device will be considered the internal device for illustrative purposes.
Each digital ASIC has at least one internal system clock. The system clock determines the speed at which the ASIC performs logic operations. When the ASIC is running on the system clock, internal registers receive data from the microprocessor operating off of the system clock or from an external device operating asynchronously. While the system clock is operating, external (asynchronous) signals used to access or update the ASIC are synchronized to the system clock. To save power, however, the system clock can be turned off, i.e., when the peripheral device goes into low-power mode. When the ASIC is in low-power mode, all accesses from the external device must be executed asynchronously.
A potential problem exists, however, when switching from synchronous operation to asynchronous operation because there is a delay of approximately 3 to 4 clock cycles for an external event to be synchronized to the system clock. This delay is referred to as the xe2x80x9csynchronization time.xe2x80x9d
If the ASIC is switched from synchronous (clocked) to asynchronous operation during the synchronization time, data being sent from an external device to one of the ASIC""s internal registers may be lost. It is, therefore, desirable to provide an ASIC that does not lose any data as a result of a switch from synchronous operation to asynchronous operation.
Circuitry that receives data on an asynchronous communications bus from an external device and receives data from a synchronous internal device is provided. The circuitry, which preferably is an integrated circuit chip, is capable of switching from synchronous operation to asynchronous operation without any loss of data.
The circuitry comprises: a register for receiving the data from the communications bus and for receiving the data from the internal device; event detection and synchronization logic for determining if there is activity on the communications bus and synchronizing such activity if detected during asynchronous operation; data capture and multiplexing logic for capturing data from the communications bus and transmitting the captured data to the register during synchronous operation; and clock switching logic.
The circuitry operates off of a system clock and each event of the activity on the communications bus has both asynchronous data and an asynchronous event signal. The clock switching logic allows the register to be updated with the system clock when the system clock is on, and when no activity on the communications bus is detected, switches the system clock off and enables the asynchronous event signal from the communications bus to update the register. Additionally, the circuitry does not switch off the system clock while there is activity on the communications bus from the external device.
Preferably, with the circuitry of the present invention, the communications bus has a minimum event time greater than the time for one and a half cycles of the system clock plus enough timing margin for an asynchronous update to occur.
A method of switching the operation of an integrated circuit chip from synchronous operation to asynchronous operation without losing any data from an external communications bus also is disclosed. The method comprises the following steps: when the chip receives a request to switch to a low-power mode from a device in which the chip operates, sampling the communications bus for any activity, each event of which has both asynchronous data and an asynchronous event signal; if activity is detected; remaining in a normal-power mode until the activity is synchronized and completed; and when no activity on the communications bus is detected, switching to low-power mode.
Preferably, the step of switching to low-power mode comprises the following steps: turning off a system clock, which runs at least one register on the chip; selecting any data from the communications bus to feed to the at least one register, the data being part of any activity on the communications bus that takes place since beginning to switch to low-power mode; and for each event, enabling the asynchronous event signal to update the register.